SC28L92 datasheet(39/73 Pages) NXP

39 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

39 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

7.3.4.2

Status Register channel B (SRB)

[1]

These status bits are appended to the corresponding data character in the receive FIFO. A read of the

status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a

reset error status command. In character mode they are discarded when the corresponding data character

is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must

used to clear block error conditions.

The bit deﬁnitions for this register are identical to the bit deﬁnitions for SRA, except that all

status applies to the channel B receiver and transmitter and the corresponding inputs and

outputs.

7.3.5 Output Conﬁguration Control Register (OPCR)

This register controls the signal presented by the OP[7:2] pins. The signal presented by

the OP[1:0] pins is controlled by the Rx, Tx, and the command register. The default

condition of the OP pins is to drive the complement of the data in the OPR[7:0] register.

When OP[7:2] pins drive DMA or interrupt type signals, they switch to open-drain

conﬁguration. Otherwise, they drive strong logic 0 or logic 1 levels.

Table 43.

SRB - Status register channel B (address 0x9) bit allocation

received

break[1]

framing

error[1]

parity

error[1]

overrun

error

TxEMTB

TxRDYB

RxFULLB

RxRDYB

Table 44.

OPCR - Output conﬁguration control register (address 0xD) bit allocation

conﬁgure

OP7

conﬁgure

OP6

conﬁgure

OP5

conﬁgure

OP4

conﬁgure OP3

conﬁgure OP2

Table 45.

OPCR - Output conﬁguration control register (address 0xD) bit description

Bit

Symbol

Description

OP7 output select

0 = The complement of OPR[7]

1 = The channel B transmitter interrupt output which is the complement of

ISR[4]. When in this mode OP7 acts as an open-drain output. Note that

this output is not masked by the contents of the IMR.

OP6 output select

0 = The complement of OPR[6]

1 = The channel A transmitter interrupt output which is the complement of

ISR[0]. When in this mode OP6 acts as an open-drain output. Note that

this output is not masked by the contents of the IMR.

OP5 output select

0 = The complement of OPR[5]

1 = The channel B receiver interrupt output which is the complement of

ISR[5]. When in this mode OP5 acts as an open-drain output. Note that

this output is not masked by the contents of the IMR.

OP4 output select

0 = The complement of OPR[4]

1 = The channel A receiver interrupt output which is the complement of

ISR[1]. When in this mode OP4 acts as an open-drain output. Note that

this output is not masked by the contents of the IMR.

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