ADP1882ARMZ-0.3-R7 datasheet(36/40 Pages) AD

36 / 40 page

ADP1882/ADP1883

Rev. 0 | Page 36 of 40

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should

be separate from the main power ground plane (PGND). With

the shortest path possible, connect the analog ground plane to

the GND pin (Pin 4). This plane should be on only the top layer

of the evaluation board. To avoid crosstalk interference, there

should not be any other voltage or current pathway directly

below this plane on Layer 2, Layer 3, or Layer 4. Connect the

negative terminals of all sensitive analog components to the

analog ground plane. Examples of such sensitive analog com-

ponents include the bottom resistor of the resistor divider, the

high frequency bypass capacitor for biasing (0.1 μF), and the

compensation network.

Mount a 1 μF bypass capacitor directly across VDD (Pin 5) and

PGND (Pin 7). In addition, a 0.1 μF should be tied across VDD

(Pin 5) and GND (Pin 4).

POWER SECTION

As shown in Figure 84, an appropriate configuration to localize

large current transfer from the high voltage input (VIN) to the out-

put (VOUT), and then back to the power ground, puts the VIN

plane on the left, the output plane on the right, and the main power

ground plane in between the two. Current transfers from the

input capacitors to the output capacitors, through Q1/Q2, during

the on state (see Figure 88). The direction of this current (yellow

arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns on.

When Q3/Q4 turns on, the current direction continues to be

maintained (red arrow) as it circles from the power ground

terminal of the bulk capacitor to the output capacitors, through

the Q3/Q4. Arranging the power planes in this manner minimizes

the area in which changes in flux occur if the current through

Q1/Q2 stops abruptly. Sudden changes in flux, usually at the

source terminals of Q1/Q2 and the drain terminals of Q3/Q4,

cause large dV/dt’s at the SW node.

VOUT

VIN

PGND

LAYER 1: SENSE LINE FOR SW

(DRAIN OF LOWER MOSFET)

LAYER 1: SENSE LINE FOR PGND

(SOURCE OF LOWER MOSFET)

Figure 88. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

The SW node is near the top of the evaluation board. The SW

node should use the least amount of area possible and be kept

away from any sensitive analog circuitry and components because

this is where most sudden changes in flux density occur. When

possible, replicate this pad onto Layer 2 and Layer 3 for thermal

relief and eliminate any other voltage and current pathways directly

beneath the SW node plane. Populate the SW node plane with

vias, mainly around the exposed pad of the inductor terminal and

around the perimeter of the source of Q1/Q2 and the drain of

Q3/Q4. The output voltage power plane (VOUT) is at the right-

most end of the evaluation board. This plane should be replicated,

descending down to multiple layers with vias surrounding the

inductor terminal and the positive terminals of the output bulk

capacitors. Ensure that the negative terminals of the output

capacitors are placed close to the main power ground (PGND),

as previously mentioned. All of these points form a tight circle

(component geometry permitting) that minimizes the area of

flux change as the event switches between D and 1 − D.

DIFFERENTIAL SENSING

Because the ADP1882/ADP1883 operate in valley current-

mode control, a differential voltage reading is taken across the

drain and source of the lower-side MOSFET. The drain of the

lower-side MOSFET should be connected as close as possible to

Pin 9 (SW) of the IC. Likewise, connect the source as close as

possible to Pin 7 (PGND) of the IC. When possible, both of

these track lines should be narrow and away from any other

active device or voltage/current paths.

PGND

Figure 89. Drain/Source Tracking Tapping of the Lower-Side MOSFET for

CS Amp Differential Sensing (Yellow Sense Line on Layer 2)

Differential sensing should also be applied between the outermost

output capacitor to the feedback resistor divider (see Figure 86

and Figure 87). Connect the positive terminal of the output

capacitor to the top resistor (RT). Connect the negative terminal

of the output capacitor to the negative terminal of the bottom

resistor, which connects to the analog ground plane, as well.

Both of these track lines, as previously mentioned, should be

narrow and away from any other active device or voltage/

current paths.

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