DAC8728 datasheet(13/52 Pages) TI

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DAC8728

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SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009

TIMING CHARACTERISTICS

(1) (2) (3) (4) (5)

At –40°C to +105°C, DVDD = +5V to +5.5V, and IOVDD = +5V, unless otherwise noted.

PARAMETER

MIN

MAX

UNIT

CS width for write operation

Delay from R/W falling edge to CS falling edge

Delay from CS rising edge to R/W rising edge

Delay from address valid to CS falling edge

Delay from CS rising edge to address change

Delay from data valid to CS rising edge

Delay from CS rising to data change

CS width for read operation

Delay from R/W rising edge to CS falling edge

t10

Delay from CS rising edge to R/W falling edge

t11

Delay from address valid to CS falling edge

t12

Delay from CS rising to address change

t13

Delay from CS falling edge to data valid

t14

Delay from CS rising to data bus off (Hi-Z)

t15

Delay from CS rising edge to LDAC falling edge

t16

LDAC pulse width

t17

Delay from LDAC rising edge to next CS rising edge

t18

Delay from BUSY rising edge to next LDAC falling edge

t19

Delay from CS rising edge to next LDAC falling edge

t20

Delay from CS rising edge to BUSY falling edge

t21

Delay from LDAC falling edge to BUSY rising edge

(1)

Specified by design; not production tested.

(2)

Sample tested during the initial release and after any redesign or process changes that may affect these parameters.

(3)

Rise and fall times of all digital input signals are 3ns.

(4)

Rise and fall times of all digital outputs are 3ns for a 10pF capacitor load.

(5)

For sequential writes to the same address, there must be a minimum of 30ns between the CS rising edges.

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