TOP264EGSLASHVG datasheet(3/36 Pages) POWERINT

3 / 36 page

Rev. B 03/10

TOP264-271

www.powerint.com

Figure 2.

Functional Block Diagram (E and V Package).

PI-4511-012810

SHUTDOWN/

AUTO-RESTART

CLOCK

CONTROLLED

TURN-ON

GATE DRIVER

CURRENT LIMIT

COMPARATOR

INTERNAL UV

COMPARATOR

INTERNAL

SUPPLY

5.8 V

4.8 V

SOURCE (S)

MAX

STOP SOFT

START

CONTROL (C)

VOLTAGE

MONITOR (V)

FREQUENCY (F)

5.8 V

1 V

LEADING

EDGE

BLANKING

÷ 16

HYSTERETIC

THERMAL

SHUTDOWN

SHUNT REGULATOR/

ERROR AMPLIFIER

DRAIN (D)

ON/OFF

MAX

66k/132k

OV/

OVP

VI (LIMIT)

CURRENT

LIMIT

ADJUST

BG + VT

LINE

SENSE

SOFT START

OFF

F REDUCTION

STOP LOGIC

EXTERNAL CURRENT

LIMIT (X)

OSCILLATOR

WITH JITTER

PWM

PS(UPPER)

PS(LOWER)

SOFT START

PS(UPPER)

PS(LOWER)

PS(UPPER)

PS(LOWER)

Pin Functional Description

DRAIN (D) Pin:

High-voltage power MOSFET DRAIN pin. The internal start-up

bias current is drawn from this pin through a switched high-

voltage current source. Internal current limit sense point for

drain current.

CONTROL (C) Pin:

Error amplifier and feedback current input pin for duty cycle

control. Internal shunt regulator connection to provide internal

bias current during normal operation. It is also used as the

connection point for the supply bypass and auto-restart/

compensation capacitor.

EXTERNAL CURRENT LIMIT (X) Pin:

Input pin for external current limit adjustment remote

ON/OFF and device reset. A connection to SOURCE pin

disables all functions on this pin.

VOLTAGE MONITOR (V) Pin:

Input for OV, UV, line feed forward with DC

MAX reduction, output

overvoltage protection (OVP), remote ON/OFF. A connection to

the SOURCE pin disables all functions on this pin.

FREQUENCY (F) Pin:

Input pin for selecting switching frequency 132 kHz if connected

to SOURCE pin and 66 kHz if connected to CONTROL pin.

SOURCE (S) Pin:

Output MOSFET source connection for high voltage power return.

Primary side control circuit common and reference point.

NO CONNECTION (NC) Pin:

Internally not connected, floating potential pin.

Figure 3.

Pin Configuration (Top View).

PI-5568-083109

Exposed Pad

(Hidden)

Internally

Connected to

SOURCE Pin

E Package (eSIP-7C)

V Package (eDIP-12)

1 V

2 X

3 C

4 F

5 NC

6 D

S 12

S 11

S 10

S 9

S 8

S 7

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