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PIC18F44J50 датащи(PDF) 5 Page - Microchip Technology

номер детали PIC18F44J50
подробное описание детали  PIC18F46J50 Family Silicon Errata and Data Sheet Clarification
PDF  12 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F44J50 датащи(HTML) 5 Page - Microchip Technology

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 2010 Microchip Technology Inc.
DS80436C-page 5
PIC18F46J50 FAMILY
4. Module: 10-Bit Analog-to-Digital
Converter (ADC)
When the A/D conversion clock select bits are set
for FOSC/2 (ADCON1<2:0> = 000), the Integral
Linearity Error (EIL) parameter (A03) and Differen-
tial Linearity Error (EDL) parameter (A04) may
exceed data sheet specifications.
Work around
Select one of the alternate AD clock sources
shown in Table 3. The EIL and EDL parameters
are met for the other clocking options.
Affected Silicon Revisions
5. Module: Parallel Master Port (PMP)
When
configured
for
Parallel
Slave
Port
(PMMODEH<1:0> = 0x and PMPEN = 1), the data
bus (PMD<7:0>) may not work correctly and
incorrect data could be captured into the PMDIN1L
register.
Work around
None.
Affected Silicon Revisions
TABLE 3:
ALTERNATE ADC SETTINGS
ADCON1<2:0>
ADCS<2:0>
Clock Setting
110
FOSC/64
101
FOSC/16
100
FOSC/4
011
FRC
010
FOSC/32
001
FOSC/8
A2
A4
X
X
A2
A4
X



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