PIC32MX320F032H datasheet(21/172 Pages) MICROCHIP

21 / 172 page

Preliminary

DS61143F-page 19

PIC32MX3XX/4XX

3.0

PIC32MX MCU

The MCU module is the heart of the PIC32MX3XX/4XX

Family processor. The MCU fetches instructions,

decodes each instruction, fetches source operands,

executes each instruction, and writes the results of

instruction execution to the proper destinations.

3.1

Features

• 5-stage pipeline

• 32-bit Address and Data Paths

• MIPS32 Enhanced Architecture (Release 2)

- Multiply-Accumulate and Multiply-Subtract

Instructions

- Targeted Multiply Instruction

- Zero/One Detect Instructions

- WAIT Instruction

- Conditional Move Instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- GPR shadow registers to minimize latency

for interrupt handlers

- Bit field manipulation instructions

• MIPS16e™ Code Compression

- 16-bit encoding of 32-bit instructions to

improve code density

- Special PC-relative instructions for efficient

loading of addresses and constants

- SAVE & RESTORE macro instructions for

setting up and tearing down stack frames

within subroutines

- Improved support for handling 8 and 16-bit

data types

• Simple Fixed Mapping Translation (FMT)

mechanism

• Simple Dual Bus Interface

- Independent 32-bit address and data busses

- Transactions can be aborted to improve

interrupt latency

• Autonomous Multiply/Divide Unit

- Maximum issue rate of one 32x16 multiply

per clock

- Maximum issue rate of one 32x32 multiply

every other clock

- Early-in iterative divide. Minimum 11 and

maximum 34 clock latency (dividend (rs) sign

extension-dependent)

• Power Control

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT

instruction)

- Extensive use of local gated clocks

• EJTAG Debug and Instruction Trace

- Support for single stepping

- Virtual instruction and data address/value

- breakpoints

- PC tracing with trace compression

FIGURE 3-1:

MCU BLOCK DIAGRAM

Note:

This data sheet summarizes the features of

the PIC32MX3XX/4XX Family of devices. It

is not intended to be a comprehensive

reference source. Refer to the “PIC32MX

Family Reference Manual” Section 2.

“MCU” (DS61113) for a detailed description

of the PIC32MX MCU. The manual is

available from the Microchip web site

(www.Microchip.com/PIC32). Resources for

the MIPS32® M4K® Processor Core are

available

www.mips.com/prod-

ucts/cores/32-bit-cores/ mips32-m4k/#.

Dual Bus I/F

System

Coprocessor

MDU

FMT

TAP

EJTAG

Power

Mgmt

Off-Chip

Debug I/F

Execution

Core

(RF/ALU/Shift)

Trace

Trace I/F

Bus Interface

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