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PCF8566P датащи(PDF) 23 Page - NXP Semiconductors |
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PCF8566P датащи(HTML) 23 Page - NXP Semiconductors |
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23 / 48 page ![]() PCF8566_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 25 February 2009 23 of 48 NXP Semiconductors PCF8566 Universal LCD driver for low multiplex rates Two displays controlled by PCF8566 can be recognized on the same I2C-bus which allows: • Up to 16 PCF8566s on the same I2C-bus for very large LCD applications (see Section 13) • The use of two types of LCD multiplex on the same I2C-bus The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the PCF8566 slave addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave address. All PCF8566s with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, one or more command bytes (m) follow which define the status of the addressed PCF8566s. The last command byte is tagged with a cleared most significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCF8566s on the bus. After the last command byte, a series of display data bytes (n) may follow. These display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8566 device. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8566. After the last display byte, the I2C-bus master issues a STOP condition (P). Fig 16. Slave address structure Fig 17. I2C-bus protocol 001aai455 S A 0 011111 0 slave address 1 byte R/W mgg390 S A 0 S 011111 0 A C COMMAND A P A DISPLAY DATA slave address acknowledge by all addressed PCF8566s acknowledge by A0, A1 and A2 selected PCF8566 only m ≥ 1 byte(s) n > 0 byte(s) 1 byte update data pointers and if necessary, subaddress counter R/W |
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