PCF2113DHSLASH4 datasheet(38/65 Pages) NXP

38 / 65 page

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

38 of 65

NXP Semiconductors

PCF2113x

LCD controllers/drivers

Also a master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges must pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge

related clock pulse (set-up and hold times must be taken into consideration).

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge bit on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

11.2.1 I2C-bus protocol

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the START procedure. The I2C-bus conﬁguration for the different PCF2113x read and

write cycles is shown in Figure 25, Figure 26 and Figure 27. The slow-down feature of the

I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the

PCF2113x.

Fig 25. Master transmits to slave receiver; write mode

mgg002

011101

slave address

CONTROL BYTE A

DATA BYTE

CONTROL BYTE A

R/W

update

data pointer

1 byte

≥ 0 bytes

DATA BYTE

acknowledgement

from PCF2113x

011101

PCF2113x

slave address

R/W

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