PCA9541A_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 16 July 2009

17 of 41

NXP Semiconductors

PCA9541A

[1]

Default values are the same for PCA9541A/01 and PCA9541A/03.

[2]

Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:

INT_IN lines goes HIGH for INTIN bit

TESTON bit is cleared for MYTEST bit

NTESTON bit is cleared for NMYTEST bit

[3]

Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master.

[4]

BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the

register gets cleared on the second clock pulse during the read operation.

[5]

If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been

masked).

8.5 Power-on reset

internal registers are initialized to their default states, with:

Channel 0 and the downstream slave channel are connected together.

connected to the downstream channel. The device is ready to receive a START

condition and its address by a master.

If either register writes to its Control Register, then the connection between the

upstream and the downstream channels is determined by the values on the Control

Registers.

2

BUSOK[4]

R only

0*

no interrupt generated by bus sensor function

1

interrupt generated by bus sensor function (masked when bus

recovery/initialization requested) - Bus was not idle when the switch occurred

1

BUSINIT[4]

R only

0*

no interrupt generated by the bus recovery/initialization function

1

interrupt generated by the bus recovery/initialization function;

recovery/initialization done

0

INTIN[2]

R only

0*

no interrupt on interrupt input (INT_IN)[5]

1

interrupt on interrupt input (INT_IN)[5]

Table 14.

Legend: * default value

Bit

Symbol