PCA9540B_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 3 September 2009

4 of 22

NXP Semiconductors

PCA9540B

6.

Functional description

Refer to Figure 1 “Block diagram of PCA9540B”.

6.1 Device addressing

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9540B is shown in Figure 5.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9540B which will be stored in the Control register. If multiple bytes are

received by the PCA9540B, it will save the last byte received. This register can be written

6.2.1 Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the Control

register. This register is written after the PCA9540B has been addressed. The 2 LSBs of

the control byte are used to determine which channel is to be selected. When a channel is

This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of connection.

Fig 5.

Slave address

R/W

002aae716

1

1

1

0

0

0

0

slave address

fixed

Fig 6.

Control register

002aae717

X

X

X

X

X

B2

B1

B0

channel selection bits

(read/write)

76543210

enable bit