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Copyright © 2009 Future Technology Devices International Limited

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Document Reference No.: FT_000017

VDIP2 Vinculum VNC1L Module Datasheet Version 1.0

Clearance No.: FTDI# 145

3.7 Signal Descriptions - Parallel FIFO Interface

The Parallel FIFO interface I/O pin description of the VNC1L device is shown in Table 3.8

Pin No.

Name

Type

Description

14

D0

I/O

FIFO Data Bus Bit 0

16

D1

I/O

FIFO Data Bus Bit 1

17

D2

I/O

FIFO Data Bus Bit 2

18

D3

I/O

FIFO Data Bus Bit 3

19

D4

I/O

FIFO Data Bus Bit 4

20

D5

I/O

FIFO Data Bus Bit 5

21

D6

I/O

FIFO Data Bus Bit 6

22

D7

I/O

FIFO Data Bus Bit 7

23

RXF#

OUTPUT

When high, do not read data from the FIFO. When low, there is data

available in the FIFO which can be read by stro bing RD# low, then high

again.

24

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data can be

written into the

FIFO by strobing WR high, then low.

25

RD#

INPUT

Enables the current

FIFO data byte on D0...D7 when low. Fetched the

next FIFO data byte (if avail- able) fro m the recei ve FIFO buffer w hen

RD# goes fro m high to low

27

WR

INPUT

Writes the data byte on the D0...D7 pins into the transmit FIFO buffer

when WR goes from high to low.

Table 3.8 - Default Interface I/O Pin Configuration Option – Paralle FIFO Interface