PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

17 of 25

NXP Semiconductors

PCA9502

Table 17.

SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

All output load = 25 pF, unless otherwise specified.

Symbol

Parameter

Conditions

Unit

Min

Max

Min

Max

CS HIGH to SO 3-state delay time

-

100

-

100

ns

CS to SCLK setup time

100

-

100

-

ns

CS to SCLK hold time

20

-

20

-

ns

SCLK fall to SO valid delay time

-

25

-

20

ns

SI to SCLK setup time

10

-

20

-

ns

SI to SCLK hold time

10

-

10

-

ns

SCLK period

83

-

67

-

ns

SCLK HIGH time

30

-

25

-

ns

SCLK LOW time

30

-

25

-

ns

CS HIGH pulse width

200

-

200

-

ns

SPI output data valid time

200

-

200

-

ns

SPI interrupt clear time

200

-

200

-

ns

Fig 16. Detailed SPI-bus timing

SO

SI

SCLK

CS

002aac429

R/W = 0; A[3:0] = IOState (0x0B)

Fig 17. SPI write IOState to GPIO switch

SI

A1

A2

A3

R/W

SCLK

0

A0

X

0

002aab878

GPIOn

D6

D7

D4

D5

D2

D3

D0

D1

CS