LPC2212 datasheet(8/45 Pages) NXP

8 / 45 page

LPC2212_2214_4

Product data sheet

Rev. 04 — 3 January 2008

8 of 45

NXP Semiconductors

LPC2212/2214

16/32-bit ARM microcontrollers

P0[30]/AIN3/EINT3/

CAP0[0]

AIN3 — ADC, input 3. This analog input is always connected to its pin.

EINT3 — External interrupt 3 input.

CAP0[0] — Capture input for Timer 0, channel 0.

P1[0] to P1[31]

I/O

Port 1 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 1 pins depends upon the pin function selected

via the Pin Connect Block.

Pins 2 through 15 of port 1 are not available.

P1[0]/CS0

LOW-active Chip Select 0 signal.

(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)

P1[1]/OE

LOW-active Output Enable signal.

P1[16]/TRACEPKT0

Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1[17]/TRACEPKT1

Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1[18]/TRACEPKT2

Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1[19]/TRACEPKT3

Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1[20]/TRACESYNC

102

Trace Synchronization; standard I/O port with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to

operate as Trace port after reset.

P1[21]/PIPESTAT0

Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P1[22]/PIPESTAT1

Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P1[23]/PIPESTAT2

Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1[24]/TRACECLK

Trace Clock. Standard I/O port with internal pull-up.

P1[25]/EXTIN0

External Trigger Input. Standard I/O with internal pull-up.

P1[26]/RTCK

I/O

Returned Test Clock output. Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Bidirectional pin

with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to

operate as Debug port after reset.

P1[27]/TDO

144

Test Data out for JTAG interface.

P1[28]/TDI

140

Test Data in for JTAG interface.

P1[29]/TCK

126

Test Clock for JTAG interface. This clock must be slower than 1

⁄6 of the CPU

clock (CCLK) for the JTAG interface to operate.

P1[30]/TMS

113

Test Mode Select for JTAG interface.

P1[31]/TRST

Test Reset for JTAG interface.

P2[0] to P2[31]

I/O

Port 2 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 2 pins depends upon the pin function selected

via the Pin Connect Block.

P2[0]/D0

I/O

External memory data line 0.

P2[1]/D1

105

I/O

External memory data line 1.

P2[2]/D2

106

I/O

External memory data line 2.

P2[3]/D3

108

I/O

External memory data line 3.

P2[4]/D4

109

I/O

External memory data line 4.

P2[5]/D5

114

I/O

External memory data line 5.

P2[6]/D6

115

I/O

External memory data line 6.

Table 3.

Pin description …continued

Symbol

Type Description

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