LPC2104FBD48SLASH00 datasheet(29/41 Pages) NXP

29 / 41 page

LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

29 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (+25

°C), nominal supply voltages.

[2]

Internal rail.

[3]

External rail.

[4]

Including voltage on outputs in 3-state mode.

[5]

VDD(3V3) supply voltages must be present.

[6]

3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[7]

Accounts for 100 mV voltage drop in all supply lines.

[8]

Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[9]

Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.

[10] Applies to P0[31:22].

[11] SPI is enabled and SSP is disabled in the PCONP register (

see LPC2104/2105/2106 user manual).

[12] To VSS.

8.1 Power consumption measurements for LPC2104/2105/2106/01

The power consumption measurements represent typical values for the given conditions.

The peripherals were enabled through the PCONP register, but for these measurements

the peripherals were not conﬁgured to run. Power measurements with all peripherals

enabled were performed with the SPI enabled and the SSP disabled. Peripherals were

disabled through the PCONP register. Refer to the

LPC2104/2105/2106 User Manual for a

description of the PCONP register.

Oscillator pins

Vi(XTAL1)

input voltage on pin XTAL1

1.8

Vo(XTAL2)

output voltage on pin

XTAL2

1.8

Table 9.

Static characteristics …continued

Tamb =0 °C to +70 °C for commercial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK

⁄4;

Tamb =25 °C; core voltage 1.8 V.

Fig 5.

Typical LPC2104/2105/2106/01 IDD(act) measured at different frequencies

frequency (MHz)

002aad709

IDD(act)

(mA)

all peripherals enabled

all peripherals disabled

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