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09HSI-S042-R0-CHT датащи(PDF) 33 Page - Hirose Electric |
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09HSI-S042-R0-CHT датащи(HTML) 33 Page - Hirose Electric |
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33 / 71 page ![]() Signal Integrity Report – IT3 (17mm) Page 33 Figure 56 TDR and TDT waveforms @120ps rise time (20% to 80%) and 2.625GHz for pair 4 of IT3-17mm for 60% pin density configuration 20% TO 80% RISE TIME (PS) WORST PAIR-TO-PAIR NEXT (%) WORST PAIR-TO-PAIR FEXT (%) 30 0.191 0.298 60 0.106 0.167 120 0.050 0.074 Table 8 Summary of Time-domain SDD for pair 4 of IT3-17mm for 60% pin density configuration 3.2.3.3 50% density pin assignment Figure 57 - Figure 59 show the TDR and TDT waveforms at 30ps, 60ps and 120ps rise times (20% to 80%) for pair 4 of IT3-17mm for 50% pin density configuration. The worst cross-talk values to the center pair are summarized in Table 9. |
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