46

DS470F4

CS8415A

16.REVISION HISTORY

Release

Date

Changes

PP1

November 1999

1st Preliminary Release

PP2

November 2000

2nd Preliminary Release

PP3

May 2001

3rd Preliminary Release

PP4

January 2003

4th Preliminary Release

F1

January 2004

Final Release

Updated “Appendix C: PLL Filter” on page 41 to include information from errata

ER470E2

F2

August 2004

-Added lead-free device ordering information.

F3

December 2004

-Changed format of Figure 6 on page 14.

-Corrected AES3 Direct (Out) format in Figure 6 on page 14 and text reference to

AES3 Direct on page 13.

-Corrected bit 0 of regitster 04h to default to 0 on page 22.

-Changed description of DETC and DETU bits in “Control Port Register Bit Defini-

tions” on page 21.

-Removed reference to Block Mode from DETU and DETUI on page 24 and

page 27.

F4

August 2005

-Updated “Ordering Information” on page 2.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

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