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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC1610S датащи(PDF) 21 Page - NXP Semiconductors |
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ADC1610S датащи(HTML) 21 Page - NXP Semiconductors |
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21 / 38 page  ADC1610S_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Objective data sheet Rev. 02 — 12 April 2010 21 of 38 NXP Semiconductors ADC1610S series ADC1610S series; CMOS or LVDS DDR digital output 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 21. The common-mode voltage of the differential input stage is set via internal 5 k Ω resistors. a. Sine clock input b. Sine clock input (with transformer) c. LVDS clock input d. LVPECL clock input Fig 19. Differential clock input Sine clock input CLKP CLKM 005aaa173 Sine clock input CLKP CLKM 005aaa054 005aaa055 LVDS clock input CLKP CLKM LVPECL clock input 005aaa172 CLKP CLKM Fig 20. Equivalent input circuit CLKP CLKM 005aaa056 PACKAGE ESD PARASITICS 5 k Ω 5 k Ω Vcm(clk) SE_SEL SE_SEL |
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