74LVC595A_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 29 May 2007

8 of 19

NXP Semiconductors

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

enable time

OE to Qn; see Figure 12

[3]

-

17.9

-

-

-

ns

2.0

6.4

14.1

2.0

16.2

ns

1.5

4.2

8.0

1.5

9.2

ns

1.5

4.5

7.6

1.5

8.7

ns

1.2

3.8

6.7

1.2

7.7

ns

disable time

OE to Qn; see Figure 12

[4]

-

9.6

-

-

-

ns

2.0

4.9

9.8

2.0

11.2

ns

1.2

2.8

5.8

1.2

6.6

ns

1.5

3.7

6.2

1.5

7.1

ns

1.2

3.5

5.7

1.2

6.5

ns

pulse width

SHCP, STCP HIGH or LOW;

see Figure 7 and Figure 8

6.0

2.5

-

7.0

-

ns

5.0

2.0

-

5.5

-

ns

4.5

1.5

-

5.0

-

ns

4.0

1.5

-

4.5

-

ns

MR LOW; see Figure 11

5.0

2.0

-

5.5

-

ns

4.0

1.5

-

4.5

-

ns

2.5

1.0

-

3.0

-

ns

2.5

1.0

-

3.0

-

ns

set-up time

DS to SHCP; see Figure 9

5.0

0.4

-

5.5

-

ns

4.0

0.1

-

4.5

-

ns

2.0

0

-

2.5

-

ns

2.0

−0.1

-

2.5

-

ns

MR to STCP; see Figure 10

8.0

3.5

-

8.5

-

ns

5.0

2.1

-

5.5

-

ns

4.0

1.8

-

4.5

-

ns

4.0

1.7

-

4.5

-

ns

SHCP to STCP; see Figure 8

8.0

3.5

-

8.5

-

ns

5.0

2.1

-

5.5

-

ns

4.0

1.8

-

4.5

-

ns

4.0

1.7

-

4.5

-

ns

Table 7.

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C Unit

Min

Max

Min

Max