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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PAM1707BZKB4 датащи(PDF) 81 Page - Texas Instruments |
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PAM1707BZKB4 датащи(HTML) 81 Page - Texas Instruments |
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81 / 155 page  RMII_MHz_50_CLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 1 2 3 5 5 4 6 7 8 9 10 11 AM1705 www.ti.com SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010 Table 6-34. EMAC Control Module RAM HEX ADDRESS RANGE 0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory Table 6-35. RMII Timing Requirements No. PARAMETER MIN TYP MAX UNIT 1 tc(REFCLK) Cycle Time, REF_CLK 20 ns 2 tw(REFCLKH) Pulse Width, REF_CLK High 7 13 ns 3 tw(REFCLKL) Pulse Width, REF_CLK Low 7 13 ns 6 tsu(RXD-REFCLK) Input Setup Time, RXD Valid before REF_CLK High 4 ns 7 th(REFCLK-RXD) Input Hold Time, RXD Valid after REF_CLK High 2 ns 8 tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before REF_CLK High 4 ns 9 th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after REF_CLK High 2 ns 10 tsu(RXER-REFCLK) Input Setup Time, RXER Valid before REF_CLK High 4 ns 11 th(REFCLKR-RXER) Input Hold Time, RXER Valid after REF_CLK High 2 ns Table 6-36. RMII Timing Requirements No. PARAMETER MIN TYP MAX UNIT 4 td(REFCLK-TXD) Output Delay Time, REF_CLK High to TXD Valid 2.5 13 ns 5 td(REFCLK-TXEN) Output Delay Time, REF_CLK High to TXEN Valid 2.5 13 ns Figure 6-25. RMII Timing Diagram Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 81 Submit Documentation Feedback Product Folder Link(s): AM1705 |
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