X84041

2

A Write Protect (

WP) pin provides hardware protection

against inadvertent writes to the memory.

tions requiring extended endurance. Inherent data re-

tention is greater than 100 years.

PIN DESCRIPTIONS

Chip Enable (

CE)

The Chip Enable input must be LOW to enable all read/

write operations. When

CE is HIGH, the chip is dese-

lected, the I/O pin is in the high impedance state, and

unless a nonvolatile write operation is underway, the

X84041 is in the standby power mode.

Output Enable (

OE)

The Output Enable input must be LOW to enable the

output buffer and to read data from the X84041 on the

I/O line.

Write Enable (

WE)

The Write Enable input must be LOW to write either data

or command sequences to the X84041.

Data In/Data Out (I/O)

Data and command sequences are serially written to or

serially read from the X84041 through the I/O pin.

Write Protect (

WP)

When the Write Protect input is LOW, nonvolatile writes

to the X84041 are disabled. When

WP is HIGH, all

functions, including nonvolatile writes, operate normally.

If a nonvolatile write cycle is in progress,

WP going LOW

will have no effect on the cycle already underway, but

will inhibit any additional nonvolatile write cycles.

DEVICE OPERATION

interface directly with most microprocessor buses. Stan-

dard

CE, OE, and WE signals control the read and write

operations, and a single l/O line is used to send and

receive data and commands serially.

Data Timing

Data input on the l/O line is latched on the rising edge of

either

WE or CE, whichever occurs first. Data output on

the l/O line is active whenever both

OE and CE are LOW.

Care should be taken to ensure that

WE and OE are

never both LOW while

CE is LOW.

Read Sequence

A read sequence consists of sending a 16-bit address

followed by the reading of data serially. The address is

written by issuing 16 separate write cycles (

WE and CE

LOW,

OE HIGH) to the part without a read cycle be-

tween the write cycles. The address is sent serially, most

significant bit first, over the I/O line. Note that this

sequence is fully static, with no special timing restric-

tions, and the processor is free to perform other tasks on

the bus whenever the X84041

CE pin is HIGH. Once the

16 address bits are sent, a byte of data can be read on

the I/O line by issuing 8 separate read cycles (

OE and

CE LOW, WE HIGH). At this point, issuing a reset

sequence will terminate the read sequence, otherwise

the X84041 will await further reads in the sequential

read mode.

Sequential Read

The byte address is automatically incremented to the

next higher address after each byte of data is read. The

data stored in the memory at the next address can be

read sequentially by continuing to issue read cycles.

When the highest address is reached ($1FF), the ad-

dress counter rolls over to address $000 and reading

may be continued indefinitely.

Reset Sequence

The reset sequence resets the X84041 and sets an

internal write enable latch. A reset sequence can be sent

at any time by performing a read/write “0”/read se-

quence (see Figs. 1 and 2). This sequence breaks the

multiple read or write cycle sequences that are normally

used when reading from or writing to the part. This

sequence can be used at any time to interrupt or end a

sequential read or page load. As soon as the write “0”

cycle is complete, the part is reset (unless a nonvolatile

write cycle is in progress). The second read cycle in this

sequence, and any further read cycles, will read a HIGH

on the l/O pin until a valid read sequence is issued. The

reset sequence must be issued at the beginning of both

read and write sequences to be sure the X84041

initiates these operations properly.