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X68C64PI датащи(PDF) 9 Page - Xicor Inc. |
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X68C64PI датащи(HTML) 9 Page - Xicor Inc. |
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9 / 12 page ![]() X68C64 9 E Controlled Write Cycle Symbol Parameter Min. Max. Units PWASH Address Strobe Pulse Width 80 ns tASL Address Setup Time 20 ns tAHL Address Hold Time 30 ns tDSW Data Setup Time 50 ns tDHW Data Hold Time 30 ns tCSL CE Setup Time 7 ns PWEH E Pulse Width 120 ns tWC Write Cycle Time 5 ms tES Enable Setup Time 30 ns tRWS R/ W Setup Time 20 ns tEH E Hold Time 20 ns tBLC Byte Load Time (Page Write) 0.5 100 µs 3868 PGM T10 E Controlled Write Cycle 3868 FHD F06.1 Note: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. AS A/D0–A/D7 A8–A12 R/W AIN DIN 3868 FHD F06 PWASH CE tCSL tASL tAHL A8–A12 tES tDSW tDHW PWEH tRWS tEH tEH tEH E |
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