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X28C64 датащи(PDF) 13 Page - Xicor Inc. |
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X28C64 датащи(HTML) 13 Page - Xicor Inc. |
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13 / 25 page ![]() X28C64 13 WRITE CYCLE LIMITS Symbol Parameter Min.(7) Typ.(1) Max. Units tWC(5) Write Cycle Time 5 10 ms tAS Address Setup Time 0 ns tAH Address Hold Time 100 ns tCS Write Setup Time 0 ns tCH Write Hold Time 0 ns tCW CE Pulse Width 100 ns tOES OE HIGH Setup Time 10 ns tOEH OE HIGH Hold Time 10 ns tWP WE Pulse Width 100 ns tWPH WE HIGH Recovery 200 ns tWPH2(6) SDP WE Recovery 1 µs tDV Data Valid 1 µs tDS Data Setup 50 ns tDH Data Hold 10 ns tDW Delay to Next Write 10 µs tBLC(7) Byte Load Cycle 1 100 µs 3853 PGM T11.1 WE Controlled Write Cycle 3853 FHD F06 Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. (6) tWPH is the normal page write operation WE recovery time. tWPH2 is the WE recovery time needed only after the end of issuing the three-byte SDP command sequence and before writing the first byte of data to the array. Refer to Figure 6 which illustrates the tWPH2 requirement. (7) For faster tWC and tBLC times, refer to X28HC64. ADDRESS tAS tWC tAH tOES tDV tDS tDH tOEH CE WE OE DATA IN DATA OUT HIGH Z DATA VALID tCS tCH tWP |
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