WM8740

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 1.7 July 2000

8

NORMAL SAMPLE RATE

In normal mode, the data is input serially on one pin for both left and right channels.

Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word

length) that were clocked in prior to the transition on LRCIN are valid.

Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in

as the first 20 or 24 bits after a transition on LRCIN.

For the three I

except with one additional preceding clock cycle.

LRCIN (PIN 1)

16-BIT RIGHT

JUSTIFIED

DIN (PIN 2)

20-BIT RIGHT

JUSTIFIED

DIN (PIN 2)

24-BIT RIGHT

JUSTIFIED

DIN (PIN 2)

24-BIT LEFT

JUSTIFIED

DIN (PIN 2)

20-BIT LEFT

JUSTIFIED

DIN (PIN 2)

BCKIN (PIN 3)

B2

B1

B0

B2

B1

B0

B2 B1

B0

B0

B0

B23 B22 B21

B19 B18 B17

B23 B22 B21 B20 B19

B4

B3

B2

B1

B0

B0

B19 B18 B17

B15

B2

B1

B0

B2

B1

B0

B2

B1

B0

B23 B22 B21

B19 B18 B17

B0

B4

B3

B2

B1

B0

B23 B22 B21 B20 B19

B19 B18 B17

B15

B2

B1

B0

B2

B1

B0

B2

B1

B0

RIGHT

LEFT

1/fs

LRCIN (PIN 1)

DIN (PIN 2)

DIN (PIN 2)

DIN (PIN 2)

BCKIN (PIN 3)

B2

B1

B0

B0

B2

B1

B0

B3

B2

B1

RIGHT

LEFT

B15

B23

B19

B6

B5

B4

B2

B1

B0

B3

B2

B1

B15

B23

B19

B6

B5

B4

B0

B2

B1

B0

B23

B19

B15

Figure 4 Audio Data Input Format