WM8716

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 3.1 April 2001

14

DE-EMPHASIS SAMPLE RATE

SF1

(REG3, B7)

SF0

(REG3, B6)

SAMPLE RATE

0

0

No de-emphasis

0

1

48kHz

1

0

44.1kHz

1

1

32kHz

Table 17 De-Emphasis Sample Rate

INFINITE ZERO DETECT

IZD

(REG3, B8)

L

Zero detect mute off

H

Zero detect mute on

Table 18 Infinite Zero Detect

DIFFERENTIAL MONO MODE

Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed

stereo, mono left or mono right, as shown in Table 19.

DIFF[1:0]

B[4:5])

DIFFERENTIAL OUTPUT MODE

00

Stereo

01

Stereo reverse.

10

Mono left – differential outputs.

VOUTL is left channel.

VOUTR is the negative of left channel.

11

Mono right – differential outputs.

VOUTL is the negative right channel.

VOUTR is right channel.

Table 19 Differential Output Modes

Using these controls a pair of WM8716 devices may be used to build a ‘dual differential’ stereo

implementation with higher performance and differential output.

CLOCK LOSS DETECTOR DISABLE

CDD (REG4, B6)

L

Clock loss detector on

R

Clock loss detector off

Table 20 Clock Loss Detector Disable

When the system clock is inactive for approximately 100

µs, the clock loss detector circuit detects the

loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.

Setting the CDD bit disables this behaviour.