WM8192

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WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

6

INPUT VIDEO SAMPLING

MCLK

VSMP

INPUT

VIDEO

t

PER

t

VSMPSU

t

VSMPH

t

VSU

t

VH

t

RSU

t

RH

t

MCLKL

t

MCLKH

Figure 1 Input Video Timing

Note:

1.

See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.

Test Conditions

°C, MCLK = 12MHz unless otherwise stated

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

83.3

ns

MCLK high period

37.5

ns

MCLK low period

37.5

ns

VSMP set-up time

10

ns

VSMP hold time

5ns

Video level set-up time

15

ns

Video level hold time

5ns

Reset level set-up time

15

ns

Reset level hold time

5ns

Notes:

1.

2.

Parameters are measured at 50% of the rising/falling edge.

OUTPUT DATA TIMING

MCLK

OP[7:0]

t

PD

Figure 2 Output Data Timing