WM8190

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

2

PIN CONFIGURATION

ORDERING INFORMATION

DEVICE

TEMP. RANGE

PACKAGE

XWM8190CDW/V

0 to 70

28-pin SOIC

SEN

OP[1]

OP[0]

SCK

SDI

DVDD2

OP[7]/SDO

OP[2]

OP[3]

OP[4]

OP[5]

OP[6]

GINP

AGND1

VRB

VRT

VRX

VRLC/VBIAS

BINP

AVDD

DGND

AGND2

DVDD1

OEB

VSMP

RLC/ACYC

MCLK

RINP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIN DESCRIPTION

PIN

NAME

TYPE

DESCRIPTION

1

RINP

Analogue input

Red channel input video.

2

AGND2

Supply

Analogue ground (0V).

3

DVDD1

Supply

Digital supply (5V) for logic and clock generator. This must be operated at the same

potential as AVDD.

4

OEB

Digital input

Output Hi-Z control, all digital outputs disabled when OEB = 1.

5

VSMP

Digital input

Video sample synchronisation pulse.

6

RLC/ACYC

Digital input

RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if

used on every pixel. ACYC autocycles between R, G, B inputs.

7

MCLK

Digital input

Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or

any multiple of 2 thereafter depending on input sample mode).

8

DGND

Supply

Digital ground (0V).

9

SEN

Digital input

Enables the serial interface when high.

10

DVDD2

Supply

Digital supply (5V/3.3V), all digital I/O pins.

11

SDI

Digital input

Serial data input.

12

SCK

Digital input

Serial clock.

Digital multiplexed output data bus.

ADC output data (d13:d0) and error flags (F) are available in three multiplexed

formats as shown, under the control of register bit MUXOP[1:0].

See ‘Output Formats’ description in Device Description section for further details.

8+6-bit

7+7-bit

4+4+4+2-bit

A

B

AB

AB

C

D

13

OP[0]

Digital output

d6

F

F

F

14

OP[1]

Digital output

d7

F

d7

d0

15

OP[2]

Digital output

d8

d0

d8

d1

16

OP[3]

Digital output

d9

d1

d9

d2

17

OP[4]

Digital output

d10

d2

d10

d3

d10

d6

d2

F

18

OP[5]

Digital output

d11

d3

d11

d4

d11

d7

d3

F

19

OP[6]

Digital output

d12

d4

d12

d5

d12

d8

d4

d0

20

OP[7]

Digital output

d13

d5

d13

d6

d13

d9

d5

d1

Alternatively, pin OP[7]/SDO may be used to output register read-back data when

OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device

Description section for further details.