WM2604

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 June 1999

8

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue

voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and

the input code according to the following relationship:

Output voltage =

( )

1024

CODE

V

2

REF

INPUT

OUTPUT

11

1111

1111

( )

1024

1023

V

2

REF

:

:

10

0000

0001

( )

1024

513

V

2

REF

10

0000

0000

( )

REF

REF

V

1024

512

V

2

=

01

1111

1111

( )

1024

511

V

2

REF

:

:

00

0000

0001

( )

1024

1

V

2

REF

00

0000

0000

0V

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k

Ω load

with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of code.

REFINAB and REFINCD pins have an input resistance of 10M

Ω and an input capacitance of typically

5pF. The reference voltage determines the DAC full-scale output.

HARDWARE CONFIGURATION OPTIONS

The device has two configuration options that are controlled by device pins.

DEVICE POWER DOWN

The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs overriding

their individual power down settings. This will reduce power consumption to typically 10nA. When the

power down function is released the device reverts to the DAC code set prior to power down.

SIMULTANEOUS DAC UPDATE

The NLDAC pin (Pin 3) can be held high to prevent serial word writes from updating the DAC latches. By

writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into the DAC

latches simultaneously.