BD9853AFV

Technical Note

9/16

www.rohm.com

2009.05 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

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Application component selection and settings

Determining output voltage

Output voltage is determined by dividing the resistance of the

external resistors.

VOUT＝0.8V×(1 + R2/R1)

determining the oscillation frequency

The oscillation pin is set by the resistor connected to the RT terminal (5 PIN).

0.001

0.010

0.100

1.000

10.000

1

10

100

1000

T iming Res is t a nce(k Ω)

Selecting the external MOSFET

In the BD9853AFV design, the main side (OUT1H, OUT2H) is provided with an external PCH FET, while an NCH FET is

used on the synchronous rectification side (OUT1L, OUT 2L) .

FET selection should be made in conformance with the following relative configurations for maximum drain voltage (VDSS),

maximum gate source voltage (VGS), maximum output current, on-resistance RDS (ON) and gate capacitance (Ciss) loss:

・

Maximum drain voltage (VDSS) is higher than the IC’s maximum input voltage (VIN).

・

Maximum gate source voltage is higher than the IC gate driving voltage (REGA, VCC-REGB).

・

・

The sum of on-resistance RDS (ON) and gate capacitance (Ciss) conduction loss, together with the switching loss,

must not exceed the power dissipation (pd) for the package.

FET conduction loss Phigh and Plow are defined as follows:

Phigh=Iout

(PMOS conduction loss)

Plow=Iout

(NMOS conduction loss)

Iout：output load current, RDS(ON) : FET ON resistance value, VIN : input voltage, Vout : output voltage

FET switching loss PSW is calculated as follows:

PSW=VIN/2×(tr + tf)×fosc×Iout

VIN : input voltage, tr : drain waveform rise time, tf : drain waveform fall time, fosc : oscillation frequency, lout : load current

In addition to the criteria for selecting individual MOSFET components, consideration must also be given to the

combination of the PMOS (main side) and NMOS (synchronous side) to be used. The configuration must not generate

any through current with PMOS and NMOS both ON at the same time. In order to meet this condition, the following

formula must be satisfied, where PCH, NCH MOSFET turn-on delay time is represented as tdON, MOSFET turn-off delay

time is tdOFF, and dead time is tdt.

tdt > tdON - tdOFF

The tdt turn-on is (OUTH,OUTL：H→L)70ns typ. Turn-off is OUTH,OUTL：L→H)70ns typ. Be sure to confirm that the

process delay time does not pose problem in terms of the overall MOSFET delay.

The following MOSFETs meet all of the selection criteria outlined above, and are recommended for use. Both are

manufactured by ROHM.

PCH: RSS040PO3

NCH: RSS065P03

R2

R1

INV

⑦　⑩

RT

⑤