ADP1871ARMZ-1.0-R7 datasheet(38/44 Pages) AD

38 / 44 page

ADP1870/ADP1871

Rev. 0 | Page 38 of 44

(component geometry permitting) that minimizes the area of

flux change as the event switches between D and 1 − D.

VOUT

VIN

PGND

Figure 89. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

DIFFERENTIAL SENSING

Because the ADP1870/ADP1871 operate in valley current-

mode control, a differential voltage reading is taken across the

drain and source of the lower-side MOSFET. The drain of the

lower-side MOSFET should be connected as close as possible to

the SW pin (Pin 9) of the IC. Likewise, the source should be

connected as close as possible to the PGND pin (Pin 7) of the

IC. When possible, both of these track lines should be narrow

and away from any other active device or voltage/current path.

LAYER 1: SENSE LINE FOR SW

(DRAIN OF LOWER MOSFET)

LAYER 1: SENSE LINE FOR PGND

(SOURCE OF LOWER MOSFET)

Figure 90. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS

Amp Differential Sensing (Yellow Sense Line on Layer 2)

Differential sensing should also be applied between the

outermost output capacitor to the feedback resistor divider (see

Figure 87 and Figure 88). Connect the positive terminal of the

output capacitor to the top resistor (RT). Connect the negative

terminal of the output capacitor to the negative terminal of the

bottom resistor, which connects to the analog ground plane as

well. Both of these track lines, as previously mentioned, should

be narrow and away from any other active device or voltage/

current path.

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