ADP1870ARMZ-0.3-R7 datasheet(21/44 Pages) AD

21 / 44 page

ADP1870/ADP1871

Rev. 0 | Page 21 of 44

When the desired valley current limit (ICLIM) has been determined,

the current-sense gain can be calculated as follows:

The valley current limit is programmed as outlined in Table 7

and Figure 71. The inductor chosen must be rated to handle the

peak current, which is equal to the valley current from Table 7

plus the peak-to-peak inductor ripple current (see the Inductor

Selection section). In addition, the peak current value must be

used to compute the worst-case power dissipation in the

MOSFETs (see Figure 72).

CLIM

where:

RON is the channel impedance of the lower-side MOSFET.

ACS is the current-sense gain multiplier (see Table 6 and Table 7).

INDUCTOR

CURRENT

VALLEY CURRENT-LIMIT

THRESHOLD (SET FOR 25A)

ΔI = 33%

OF 30A

COMP

OUTPUT

SWING

COMP

OUTPUT

2.4V

35A

30A

32.25A

37A

49A

39.5A

ΔI = 45%

OF 32.25A

ΔI = 65%

OF 37A

MAXIMUM DC LOAD

CURRENT

Although the ADP1870/ADP1871 have only four discrete current-

sense gain settings for a given RON variable, Table 7 and Figure 71

outline several available options for the valley current setpoint

based on various RON values.

Table 7. Valley Current Limit Program1

RON

(mΩ)

Valley Current Level

47 kΩ

22 kΩ

Open

100 kΩ

ACS = 3 V/V

ACS = 6 V/V

ACS = 12 V/V

ACS = 24 V/V

1.5

38.9

29.2

2.5

23.3

39.0

19.5

3.5

33.4

16.7

4.5

26.0

23.4

11.7

5.5

21.25

10.6

23.3

11.7

5.83

31.0

15.5

7.75

7.5

26.0

13.0

6.5

3.25

Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

HICCUP MODE DURING SHORT CIRCUIT

A current-limit violation occurs when the current across the

source and drain of the lower-side MOSFET exceeds the

current-limit setpoint. When 32 current-limit violations are

detected, the controller enters idle mode and turns off the

MOSFETs for 6 ms, allowing the converter to cool down. Then,

the controller reestablishes soft start and begins to cause the

output to ramp up again (see Figure 73). While the output

ramps up, COMP is monitored to determine if the violation is

still present. If it is still present, the idle event occurs again,

followed by the full-chip power-down sequence. This cycle

continues until the violation no longer exists. If the violation

disappears, the converter is allowed to switch normally,

maintaining regulation.

1 Refer to Figure 71 for more information and a graphical representation.

123

456789 10 11 12 13 14 15 16 17 18 19 20

RON (mΩ)

RES = 47k

Ω

ACS = 3V/V

RES = 22k

Ω

ACS = 6V/V

RES = NO RES

ACS = 12V/V

RES = 100k

Ω

ACS = 24V/V

Figure 71. Valley Current-Limit Value vs. RON of the Lower-Side MOSFET

for Each Programming Resistor (RES)

CLIM

ZERO

CURRENT

REPEATED CURRENT-LIMIT

VIOLATION DETECTED

A PREDETERMINED NUMBER

OF PULSES IS COUNTED TO

ALLOW THE CONVERTER

TO COOL DOWN

SOFT START IS

REINITIALIZED TO

MONITOR IF THE

VIOLATION

STILL EXISTS

Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation

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