Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

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7

Pin Description (continued)

PIN

NAME

MAX1065

MAX1066

MAX1065

MAX1066

FUNCTION

15

11

REFADJ

Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for

reference mode.

16

12

REF

Reference Input/Output. Bypass REF with a 1µF capacitor to AGND for internal

reference mode. External reference input when in external reference mode.

17

—

RESET

Reset Input. Logic high resets the device.

—

13

HBEN

High Byte-Enable Input. Used to multiplex the 14-bit conversion result.

1: Most significant byte available on the data bus.

0: Least significant byte available on the data bus.

18

14

CS

Convert Start. The first falling edge of

CS powers up the device and enables

acquire mode when R/

C is low. The second falling edge of CS starts

conversion. The third falling edge of

CS loads the result onto the bus when R/C

is high.

19

15

DGND

Digital Ground

20

16

Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.

21

17

N.C.

D0/D8

No Connection. Do Not Connect (MAX1065).

Three-State Digital Data Output (MAX1066).

22

18

N.C.

D1/D9

No Connection. Do Not Connect (MAX1065).

Three-State Digital Data Output (MAX1066).

23

19

D0

D2/D10

Three-State Digital Data Output

24

20

D1

D3/D11

Three-State Digital Data Output

25

—

D2

—

Three-State Digital Data Output

26

—

D3

—

Three-State Digital Data Output

27

—

D4

—

Three-State Digital Data Output

28

—

D5

—

Three-State Digital Data Output

REFERENCE

OUTPUT

REGISTERS

CLOCK

SUCCESSIVE-

APPROXIMATION

REGISTER AND

CONTROL LOGIC

CAPACITIVE

DAC

MAX1065

MAX1066

14 OR 8*

14 OR 8*

REFADJ

REF

DGND

AGND

RESET**

AIN

R/C

CS

EOC

HBEN*

AGND

D0–D13

OR

D0/D8–D5/D13*

*BYTE WIDE (MAX1066 ONLY)

**16-BIT WIDE (MAX1065 ONLY)

5k

Ω

Functional Diagram