H5GQ1H24AFR-R0C datasheet(161/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

161

H5GQ1H24AFR

7.2. ON DIE TERMINATION (ODT)

GDDR5 SGRAMs support multiple termination modes for its high speed input signals. When the termina‐

tion is enabled for a receiver, an impedance defined for that termination mode is applied between that

input receiver and the VDDQ supply rail. This is commonly referred to as VDDQ termination. Registers

have been defined to control the termination modes. ADD/CMD Termination is controlled using MR1 bits

A4 and A5. Data termination is controlled using MR1 bits A2 and A3. WCK termination is controlled

using MR3 bits A8 and A9.

Table 55 includes all the high speed GDDR5 SGRAM signals whose receivers include on die termination to

VDDQ and whether their termination can be disabled by ADD/CMD Term, DQ Term, or WCK Term. A

“Yes” indicates whether the mode register field controls termination for the signal.

Table 55. Signals Affected by Termination Control Registers

ADD/CMD Term

MR1 (A4,A5)

DQ Term

MR1 (A2,A3)

WCK Term

MR3 (A8,A9)

Signal

x32

x16

x32

x16

x32

x16

RAS#, CAS#, WE, CS#, CKE#

Yes

A10/A0, A9/A1, BA0/A2, BA3/A3,

BA2/A4, BA1/A5, A11/A6, A8/A7,

A12/RFU/(NC), ABI#

Yes

DQ[7:0], DBI0#

Yes

DQ[15:8], DBI1#

Disabled

Yes

Disabled

DQ[23:16], DBI2#

Yes

DQ[31:24], DBI3#

Disabled

Yes

Disabled

WCK01, WCK01#, WCK23, WCK23#

Yes

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