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H5GQ1H24AFR-R0C датащи(PDF) 125 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C датащи(HTML) 125 Page - Hynix Semiconductor |
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125 / 173 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 125 H5GQ1H24AFR Figure 78. Voltage Waveform Table 40 AC Operating Conditions POD15 Parameter Symbol Min Typ Max Unit Note AC Input Logic HIGH Voltage for address and command VIHA (AC) VREFC + 0.20 V AC Input Logic LOW Voltage for address and command VILA (AC) VREFC ‐ 0.20 V AC Input Logic HIGH Voltage for DQ and DBI# pins with VREFD VIHD (AC) VREFD + 0.15 V AC Input Logic LOW Voltage for DQ and DBI# pins with VREFD VILD (AC) VREFD ‐ 0.15 V AC Input Logic HIGH Voltage for DQ and DBI# pins with VREFD2 VIHD2 (AC) VREFD2 + 0.40 V AC Input Logic LOW Voltage for DQ and DBI# pins with VREFD2 VILD2 (AC) VREFD2 ‐ 0.40 V VIL (AC) VIL (DC) VREF ‐ AC Noise VREF ‐ DC Noise VREF + DC Noise VREF + AC Noise VIH (DC) VIH (AC) VOH VIN (AC) ‐ Provides margin between VOL (MAX) and VIL (AC) VDDQ VOL (MAX) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) Note: VREF, VIH, VIL refer to whichever VREFxx (VREFD, VREFD2, or VREFC) is being used. Output Input |
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