Copyright
©2009, KT Micro, Inc.
7
KT0803K
Register Bank
The register bank stores channel frequency codes, calibration parameters, operation status, mode and power
controls, which can be accessed by the internal digital controller, state machines and external micro
controllers through the serial interface.
All registers are 8 bits wide. Control logics are active high unless specifically noted.
Register
7
6
5
4
3
2
1
0
0x00
CHSEL[8:1]
0x01
RFGAIN[1:0]
PGA[2:0]
CHSEL[11:9]
0x02
CHSEL[0]
RFGAIN[3]
-
-
MUTE
PLTADJ
-
PHTCNST
0x04
MONO
PGA_LSB[1:0]
FDEV[1:0]
BASS[1:0]
0x0B
-
-
PDPA
-
-
-
-
-
0x0E
-
-
-
-
-
-
PA_BIAS
-
0x0F
-
-
-
PW_OK
-
SLNCID
-
-
0x10
-
-
-
LMTLVL[1:0]
-
-
PGAMOD
0x12
SLNCDIS
SLNCTHL[2:0]
SLNCTHH[2:0]
SW_MOD
0x13
RFGAIN[2]
-
-
-
-
PA_CTRL
-
-
0x14
SLNCTIME[2:0]
SLNCCNTHIGH[2:0]
-
-
0x16
-
-
-
SLNCCNTLOW[2:0]
Note 1: ONLY read/write the defined registers.
Note 2: Shaded registers are used in KT0803.
Register 0x00 (Address: 0x00, Default value: 0x81)
Bit
7
6
5
4
3
2
1
0
KT0803K
CHSEL[8:1]
KT0803
CHSEL[7:0]
As the minimum frequency step is changed from 100KHz in KT0803 to 50KHz in KT0803K. The 12 bits
(Reg0x1[2:0]; Reg0x0[7:0]; Reg0x2[7]) are required to select the FM transmission channel instead of 11
bits in KT0803. If a 100 KHz step is wanted, set Reg0x2[7] to 0 and thus no software change is needed
from KT0803 to KT0803K to set the same FM frequency.
Register 0x01 (Address: 0x01, Default value: 0xC3)
Bit
7
6
5
4
3
2
1
0
KT0803K
RFGAIN[1:0]
PGA[2:0]
CHSEL[11:9]
KT0803
RFGAIN[1:0]
PGA[2:0]
CHSEL[10:8]
Bits
Type
Default
Label
Description
7:6
RW
11
RFGAIN[1:0]
Transmission Range Adjustment with RFGAIN[3] in Reg
0x02[6] and RFGAIN[2] in Reg 0x13[7] (See Table 4
below)
5:3
RW
000
PGA[2:0]
PGA Gain Control (see PGA_LSB description, Reg 0x04)
111: 12dB
110: 8dB
101: 4dB
100: 0dB
000: 0dB
001: -4dB
010: -8dB
011: -12dB
2:0
RW
011
CHSEL[11:9]
FM Channel Selection[11:9]
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