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ES51999 датащи(PDF) 9 Page - Cyrustek corporation |
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ES51999 датащи(HTML) 9 Page - Cyrustek corporation |
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9 / 21 page ![]() 07/07/06 9 ES51999 4 3/4 and 5 3/4 A/D AUTO first. When oscillator is 4MHz, D0<0:19> is up to 44,000 counts. When oscillator is 10MHz, if the conversion rate is 20/sec, it counts to 220,000; if the conversion rate is not 20/sec, it counts to 440,000. - - Voltage/current with frequency (“001” & “011”) measurement: SIGN 0 BATT D0<0:19> (20 bits) D1<0:17> (18 bits) 0 1 2 3 ~ 22 23 ~ 40 SIGN For voltage/current measurement. ‘H’ for negative; ‘L’ for positive. In AC, Ω and diode measurement, this bit can be ignored. BATT ‘H’ for battery-low indication. D0<0:19> Conversion result of voltage or current measurement. D1<0:17> Conversion result of frequency measurement. - Frequency (“110”) measurement: OL UL BATT D0<0:19> (20 bits) D1<0:17> (18 bits) D2<0:5> (6 bits) 0 1 2 3 ~ 22 23 ~ 40 41 ~ 46 OL Overflow when in 40, 400 and 4000Hz ranges. UL Underflow when in 40, 400 and 4000Hz ranges. BATT ‘H’ for battery-low indication. D0<0:19>, D1<0:17>, D2<0:5> Please see the description in frequency and duty cycle measurement. (2) Dual Slope A/D—four phases timing The ES51999’s measurement cycle contains four phases, ZI, AZ, INT, and DINT. The timing will be changed as conversion rate changed. There are some examples as follow, and the others are alike. ES51999 is a dual-slope analog-to-digital converter (ADC). Figure 2.1 is a structure of dual-slope integrator. Its measurement cycle has two distinct phases: input signal integration (INT) phase and reference voltage integration (DINT) phase. In INT phase, the input signal is integrated for a fixed time period, then A/D enters DINT phase in which an opposite polarity constant reference voltage is integrated until the integrator output voltage becomes to zero. Since both the time for input signal integration and the reference voltage are fixed, the de-integration time is proportional to the input signal. Hence, we can define the mathematical equation about input signal, reference voltage integration (see Figure 2.1): |
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