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Revision 1.0

17 - 33

AS3930

Data Sheet - D e t a i l e d D e s c r i p t i o n

Figure 12. Writing of a single Byte (falling edge sampling)

Figure 13. Writing of Register Data with auto-incrementing Address

Reading of Data from Addressable Registers (READ Mode)

Once the address has been sent through SDI, the data can be fed through the SDO pin out to the microcontroller.

A CS LOW toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the READ command

and prepare the Interface to the next command control Byte.

To transfer bytes from consecutive addresses, SDI master has to keep the CS signal high and the SCLK clock has to be active as long as data

need to be read.

Figure 14. Reading of a single Register Byte

CS

SCLK

SDI

0

0

A5

A4

A3

A2

A1

A0

D5

D 4

D3

D2

D1

D0

D7

D6

X

X

SCLK raising

edge Data is

transf ered from

µC

SCLK

falling edge

Data is

sampled

Data is moved

t o Address

A5-A0

CS falling

edge signals

end of

WRITE Mode

Two leading

Zeros indicate

WRITE Mode

CS

SCLK

SDI

00

A

5

A

4

A

3

A

2

A

1

A

0

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

X

X

Data is moved

t o Address

<A5-A0 > + n

CS falling

edge signals

end of

WRITE Mode

Two leading

Zeros indicat e

WRI TE Mode

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

1

D

0

Data is moved

to Addres s

<A5-A0 > + (n- 1)

Dat a is mov ed

to Addres s

<A5-A0> +1

Data is moved

t o Address

<A5-A0>

CS

SCLK

SDI

0

1

A5

A4

A3

A2

A1

A0

X

X

SCLK rais ing

edge Data is

mov ed f rom

Address

<A5-A0>

CS falling

edge signals

end of READ

Mode

01 pattern

indicat es

READ Mode

D4

D3

D2

D1

D0

D7

D6

X

X

SDO

SCLK raising

edge Dat a is

transfered from

µC

SCLK

f alling edge

Dat a is

sampled

SCLK f alling

edge Dat a is

transf ered to

µC

D5