AS1500 datasheet(7/14 Pages) AMSCO

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AS1500

Data Sheet - El ectrical Characte ristics

AS150x – SPECIFICATIONS

VCC = 3V±10% or 5V±10%, VA = VCC, VB = 0V, –40ºC ≤ TA ≤ +125ºC unless otherwise noted.

tS_50k

VW Settling Time

RWB = 50kΩ, VA = VCC, VB = 0V,

±1% Error Band

µs

tS_100k

RWB = 100kΩ, VA = VCC, VB = 0V,

±1% Error Band

µs

eNWB_50k

Resistor Noise Voltage

RWB = 50kΩ, f =1kHz

nV/

√ Hz

eNWB_100k

RWB = 100kΩ, f =1kHz

nV/

√ Hz

1. Typicals represent average readings at 25ºC and VCC = 5V.

2. Wiper is not connected. IAB = 70µA for the 50kΩ version and 35µA for the 100kΩ version.

3. All Tempcos are guaranteed by design and not subject to production test.

4. Terminal A is not connected. IW = 70µA for the 50kΩ version and 35µA for the 100kΩ version.

5. Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6. All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance

tests are measured with 2.5V bias on the measured terminal. The remaining resistor terminals are left open cir-

cuit.

7. Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.

8. PDISS is calculated from (IDD×VCC). CMOS logic level inputs result in minimum power dissipation.

9. All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteris-

tics use VCC=5V.

Table 5. Switching Characteristics

Symbol

Parameter

Conditions

Min

Typ

1. Typicals represent average readings at 25ºC and VCC=5V.

Max

Unit

Switching Characteristics

2 3

2. Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with

2.5V bias on the measured terminal. The remaining resistor terminals are left open circuit.

3. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1ns

(10% to 90% of VCC) and timed from a voltage level of 1.6V. Switching characteristics are measured using

VCC=3V or 5V. To avoid false clocking, a minimum input logic slew rate of 1V/µs should be maintained.

tCH, tCL

Input Clock Pulsewidth

Clock Level High or Low

tDS

Data Setup Time

tDH

Data Hold Time

tCSS

CSN Setup Time

tCSWH

CSN High Pulsewidth

tCSWL

CSN Low Pulsewidth

100

tCSH

CK Fall to CSN Rise

Hold Time

0ns

tCS1

CSN Rise to Clock Rise

Setup

Table 4. Electrical Characteristics – 50k and 100k Versions

Symbol

Parameter

Conditions

Min

Typ

Max

Units

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