AS1339 datasheet(22/25 Pages) AMSCO

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AS1339

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Layout Considerations

High peak currents of up to 1.1A and a high switching frequency makes the PCB layout important. Following rules

should be considered:

- The power traces (IN1A, IN1B, IN2, LX, PAA, PAB, PGND) should be kept as short, direct and wide as practical.

- All capacitors should be placed as close as possible near the device.

- Try to keep the serial resistance (ESR) of CLDO1 and CLDO2 as low as possible.

- The negative terminations of the capacitors COUT and CIN should be kept as close to each other as possible. A

starpoint to PGND is recommended.

As shown in Figure 54 the current path between the pins IN1A/IN1B (C3/C4) and pin PGND (A4) via CIN1 is kept as

short as possible. Also the current path between the pins PAB/PAA (D3/D4) and pin PGND (A4) via COUT is very close.

The negative terminals of CIN1 and COUT are connected to pin PGND (A4) as a starpoint.

In order to keep noise emissions suppressed the connection between pin LX (B4) and the pins PAB/PAA (D3/D4) via

the coil is kept very short. A shielded coil is recommended.

To keep the influence of the DC-DC on the LDOs in terms of supply ripple and noise quite low the IN1, IN2 and AGND,

PGND path are separated in the layout. These power paths should be connected via a starpoint directly at the supply.

Figure 54. Layout for Space Limited Applications

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