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AD9575ARUZPEC датащи(PDF) 8 Page - Analog Devices

номер детали AD9575ARUZPEC
подробное описание детали  Network Clock Generator, Two Outputs
PDF  16 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9575ARUZPEC датащи(HTML) 8 Page - Analog Devices

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AD9575
Rev. 0 | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
VDDA
VDDX
XO1
GNDA
GNDX
XO2
GNDA
VDDA
16
15
14
13
12
11
10
9
GND
LVDS/LVPECL OUT
LVDS/LVPECL OUT
CMOS OUT/SEL1
GND_CMOS
VDD_CMOS
VDD
SEL0
AD9575
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 7
GNDA
Analog Ground.
2, 8
VDDA
Analog Power Supply (3.3 V).
3
VDDX
Crystal Oscillator Power Supply.
4, 5
XO1, XO2
External Crystal.
6
GNDX
Crystal Oscillator Ground.
9
GND_CMOS
Ground for LVCMOS Output.
10
CMOS OUT/SEL1
LVCMOS Output/Output Frequency Select.
11
VDD_CMOS
Power Supply for LVCMOS Output.
12
VDD
Power Supply for LVDS or LVPECL Output.
13
LVDS/LVPECL OUT
Complementary LVDS or LVPECL Output.
14
LVDS/LVPECL OUT
LVDS or LVPECL Output.
15
GND
Ground for LVDS or LVPECL Output.
16
SEL0
Output Frequency Select.
Table 12. Output Frequency Selection1
Mode
XTAL
SEL0
SEL1
LVDS/LVPECL Output
LVCMOS Output
1
25 MHz
GND
X2
100 MHz
33.33 MHz
2
25 MHz
VDD
GND
156.25 MHz
High-Z
3
25.78125 MHz
VDD
GND
161.132812 MHz
High-Z
4
25 MHz
NC
X2
125 MHz
62.5 MHz
5
25 MHz
15 kΩ pull-up
VDD
159.375 MHz
High-Z
6
25 MHz
15 kΩ pull-up
GND
312.5 MHz
High-Z
7
25 MHz
VDD
VDD
106.25 MHz
High-Z
8
19.44 MHz
VDD
No connect
155.52 MHz
High-Z
1 The AD9575 must be power-cycled if the select pin voltages are altered.
2 X = in Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS output by forcing Pin16 to GND.



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