DM562AP_07 datasheet(17/48 Pages) DAVICOM

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DM562AP

V.90 Integrated Data/ Fax/Voice/Speakerphone

Modem Device Single Chip with Memory Built in

Final

Bit1: frame end flag (read only)

1:Indicate end of HDLC frame (clear by a reset

action)

Bit2: fram ready flag (read only)

1:CRC check ok.

0:CRC check fail.

Bit3: In

_ buffer empty flag

1:In

_ buffer empty (clear automatically by a

write to In

_buffer)

0:In

_ buffer not empty

Bit7: reset bit (write only)

1:software reset

CRCL register: Address DC0AH (read only)

CRCH register: Address DC0BH (read only)

8. Micro-controller Control Register for Internal

Mode

UART Clock (internal mode only)

The internal clock of the virtual UART logic is fixed at

1.8432MHz. The clock is derived from an external

30MHz crystal. The UART 1.8432MHz clock will be

obtained by division. When the operating frequency

of the DM6588A controller changes, the divider

should be changed accordingly. This divider is

specified by the Configuration Register which can be

written by the DM6588A controller. The address

mapping of the register is D400H: (DM6588A

controller memory mapping)

Bit 0: Always 0.

Bit 6-1: define the clock divider range from 2 to 64

(even number).

Bit 7: Not used.

UART Clock Register: ( internal mode only )

Address D400H Reset State: 06H

Write Only

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

dat6

dat5

dat4

dat3

dat2

dat1

UART Baud Generator Divisor Latch Register:

Address EC00H ( internal mode only )

Read only

bit7

bit6

bit5

bit4

bit3

Bit2

bit1 bit0

dat7 dat6 dat5 dat4 dat3 Dat2 dat1 dat0

By reading this register, the micro-controller can

monitor the value of the low byte divisor latch of the

virtual UART baud generator (see DLL in next section)

and determine the baud rate clock itself.

Modem Status Control Register (MSCR):

Address E000H ( internal mode only )

Write only

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

/CTS /DSR /DCD

/RI

This register contains information about the line

status of the modem. The available signals are Ring

Detect (/RI), Carrier Detect (/DCD), Data Set Ready

(/DSR) and Clear To Send (/CTS).

9. Host Control Register for Virtual 16550A UART

(internal mode only)

Receiver Buffer (Read), Transmitter Holding

Reset State 00h

bit7

bit6

bit5

bit4

bit3

Bit2

bit1

Bit0

dat7 dat6 dat5 dat4 dat3 Dat2 dat1 Dat0

When this register address is read, it contains the

parallel received data. Data to be transmitted is

written to this register.

Interrupt Enable Register (IER): Address 1

Reset State 00h, Write Only

bit7 Bit

bit

bit4

bit3

bit2

bit1

bit0

Enable

Modem

Status

Intr

Enable

Line

Status

Intr

Enable

Holding

Intr

Enable

Data

Intr

This 8-bit register enables the four types of interrupts

as described below. Each interrupt source can

activate the INT output signal if enabled by this

UART interrupts.

Bit 0: This bit enables the Received Data Available

and timeout interrupts in the FIFO mode when

set to logic 1.

Version: DM562AP-DS-F03

Nov. 09, 2007

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