ACE5372

Low Power Real-Time Clock (RTC)

VER 1.2

13

CLEN

32KHz Clock Output Bit

⎯CLEN

Description

Operation

0

32KHz clock output enabled

Default

1

32KHz clock output disabled

By setting this bit to “0”, output of clock pulses of the same frequency as the crystal oscillator is enabled.

CTFG

Periodic Interrupt Flag Bit

CTFG

Description

Operation

0

Periodic interrupt output=OFF

Default

1

Periodic interrupt output=ON

This bit is set to “1” when periodic interrupt pulses are output (

⎯INTRA or ⎯INTRB= “L”).

The CTFG bit may be set only to “0” in the interrupt level mode. Setting this bit to “0” sets either the

⎯INTRA or

the

⎯INTRB to OFF (“H”). When this bit is set to “1” nothing happens.

AAFG, BAFG

ALARM-A, ALARM-B Flag Bit

ALARM-A，ALARM-B

Description

Operation

0

Unmatched alarm register with clock counter

Default

1

Matched alarm register with clock counter

* The alarm interruption is enabled only when the AALE, BALE bits are set to “1”. This bit turns to “1” when matched time is

sensed for each alarm.

* The AAFG, BAFG bit may be set only to “0”. Setting this bit to “0” sets either the

⎯INTRA or the

⎯ INTRB to the OFF “H”. When this bit is set to “1” nothing happens.

When the AALE, BALE bit is set to “0”, alarm operation is disabled and “0” is read from the AAFG, BAFG bit.

Output Relationships Between AAFG（BAFG）Bit and

⎯INTRA（⎯INTRB）