ST8024S

Ver 0.39

Page 27/27

2008/05/05

14.

REVISION

REVISION

DESCRIPTION

PAGE

DATE

0.10

First release

1-25

2005/9/12

0.20

Add LGND definition, and re-define the pin function

1-25

2005/11/22

0.30

Modify suggestion resistor value for V0.

Add alignment mark data, Add LCD Panel Layout Example

Modify bond pad height to 18um

21

2006/5/22

0.31

Modify bump pad height to 15um and add wafer thickness.

24

2006/6/7

0.32

Modify all Vss for logic setting pins to LGND

1-25

2006/7/21

0.33

Modify description of LGND

6-8

2006/7/21

0.34

Change Sitronix logo and modify description of LGND for

COM mode

1-25

2006/7/21

0.35

Modify pad define and size for pad No.6 and No.38.

21-24

2006/7/24

0.36

Modify Chip size and thickness with scribe line

Modify “ Output resistance” test condition

16,22,24

2006/10/26

0.37

CONDITIONS” and “ ABSOLUTE MAXIMUM RATINGS”

2,15-18

2007/1/3

0.38

Modify all the data about absolute max voltage and recommend max

voltage

2,16-18

2007/5/25

0.39

Modify the ITO resistor value suggestion

Add application note

21,26

2008/5/05

The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without

permission from Sitronix.