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ST7632 датащи(PDF) 22 Page - Sitronix Technology Co., Ltd. |
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ST7632 датащи(HTML) 22 Page - Sitronix Technology Co., Ltd. |
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22 / 96 page ![]() ST7632 Ver 1.7 22/96 2006/08/15 7-2 ACCESS TO DDRAM AND INTERNAL REGISTERS ST7632 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Fig. 7.2.1 illustrates these relations. N D(N) D(N+1) D(N+2) D(N+3) N D(N) D(N+1) D(N+2) D(N+3) N N+1 N+2 N+3 MPU signal A0 /WR DATA Internal signals /WR BUS HOLDER COLUMN ADDRESS Write Operation N Dummy D(N) D(N+1) MPU signal A0 /WR DATA Internal signals /WR COLUMN ADDRESS /RD N D(N) D(N+1) D(N+2) D(N) D(N+1) D(N+2) N /RD BUS HOLDER Read Operation Fig 7.2.1 |
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