ST7585 datasheet(17/51 Pages) SITRONIX

17 / 51 page

ST7585

Ver 1.0c

17/51

2009/04/14

Display Data RAM (DDRAM)

ST7585 contains a 66X102 bit static RAM that stores the display data. The display data RAM (DDRAM) store the dot data

for the LCD. It is an addressable array with 102 columns by 66 rows (8-page with 8-bit, 1-page with 1-bit and 1-page with

1-bit). The X-address is directly related to the column output number. Each pixel can be selected when the page and

column addresses are specified. The rows are divided into: 8 pages (page 0~7) each with 8 lines (for COM0~63), the 8

page with only 1 line (for COM64) and the 9

th page with only 1 line (the 65th row, COMS, for icon). The display data (D7~D0)

corresponds to the LCD common-line direction (D7 at top). Those pages with 8 lines can be accessed through D[7:0]

directly. When accessing those pages with fewer than 8 lines, the valid bit(s) in D[7:0] should be checked. Refer to Fig 13

for detailed illustration. The microprocessor can write to and read from (only Parallel interfaces) DDRAM by the I/O buffer.

Since the LCD controller operates independently, data can be written into DDRAM at the same time as data is being

displayed without causing the LCD flicker or data-conflict.

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by

only the

“Set Page” instruction. Page Address 9 is a special RAM area for the icons and display data is only 1-bit valid (D7).

Line Address Circuit

This circuit controls each line in DDRAM to transfer 102-bit line data to the display data latch circuit. Therefore, the content

in DDRAM can be transferred to the segment drivers, and display the content on the LCD module as shown in Fig 12. At the

beginning of each LCD frame, the 102-bit RAM data of Line-0 are transferred to the display data latch circuit. At the next

line period, the Line Address is increased by one and the 102-bit RAM data at the next line are transferred to the display

data latch circuit. The 102-bit icon data are transferred at the last line period during each frame.

Column Address Circuit

Column Address Circuit has an 8-bit preset counter that provides Column Address to the DDRAM. The display data RAM

column address is specified by the Column Address Set command. The specified column address is incremented (+1) with

each display data read/write command. This allows the MPU display data to be accessed continuously.

TMX and TMY make it possible to invert the relationship between the addresses (Line Address and Column Address) and

the outputs (COM/SEG). It is necessary to rewrite the display data into built-in RAM after changing TMX setting. The

relation between DDRAM and outputs with different TMX or TMY setting is shown below.

ST7585 датащи(PDF) 17 Page - Sitronix Technology Co., Ltd.