ST7522

Ver 1.0c

21/45

2002/07/10

Set Column Address

This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU

continuously, the column address is incremented by I each time it is accessed from the set address. Therefore, the MPU

can access to data continuously. The column address stops to be incremented at address 95, and the page address is not

changed continuously.

A0

RD

―

WR

―

D7

D6

D5

D4

D3

D2

D1

D0

0

1

0

0

0

0

0

A3

A2

A1

A0

A0

RD

―

WR

―

D7

D6

D5

D4

D3

D2

D1

D0

0

1

0

0

0

0

1

A7

A6

A5

A4

This command loads the column address register.

A7

A6

A5

A4

A3

A2

A1

A0

Column Address

0

0

0

0

0

0

0

0

0(default)

0

0

0

0

0

0

0

1

1

.

.

.

.

.

.

.

.

0

1

0

1

1

1

1

1

95

Read Status

A0

RD

―

WR

―

D7

D6

D5

D4

D3

D2

D1

D0

0

0

1

0

ADC

ON/OFF RESET

0

0

0

0

Reading the command I/O register (A0=0) yields system status information.

The ADC bit indicates the way column addresses are assigned to segment drivers.

ADC=1 : Normal. Column address n = segment driver n.

ADC=0: Inverted. Column address 95-n = segment driver n.

The ON/OFF bit indicates the current status of the display.

It is the inverse of the polarity of the display ON/OFF command.

ON/OFF=1: Display OFF

ON/OFF=0: Display ON

The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode,

RESET=1: Currently executing reset command.

RESET=0: Normal operation

Low column set

High column set