MPC8548CVTAQJ datasheet(69/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

PCI Express

16.1

DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 15.2, “SerDes Reference Clocks.”

16.2

AC Requirements for PCI Express SerDes Clocks

Table 51 lists the AC requirements for the PCI Express SerDes clocks.

16.3

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

16.4

Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer refer to PCI Express Base

Specification. Rev. 1.0a.

16.4.1

Differential Transmitter (TX) Output

Table 52 defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Unit

Notes

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles.

—

100

—

tREFPJ

Phase jitter. Deviation in edge location with respect to mean edge

location.

–50

—

Note:

1. Typical based on

PCI Express Specification 2.0.

Table 52. Differential Transmitter (TX) Output Specifications

Symbol

Parameter

Min

Nom

Max

Unit

Comments

Unit interval

399.88

400

400.12

Each UI is 400 ps ± 300 ppm. UI does not account

for spread spectrum clock dictated variations.

See Note 1.

VTX-DIFFp-p

Differential

peak-to-peak

output voltage

0.8

—

1.2

VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|. See Note 2.

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