MPC8548CVTAQJB datasheet(55/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

13.2

I2C AC Electrical Specifications

Table 46 provides the AC timing parameters for the I2C interfaces.

Table 46. I2C AC Electrical Specifications

Parameter

Symbol1

Min

Max

Unit

Notes

SCL clock frequency

fI2C

0400

kHz

—

Low period of the SCL clock

tI2CL

1.3

—

μs4

High period of the SCL clock

tI2CH

0.6

—

μs4

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs4

Hold time (repeated) START condition (after this period,

the first clock pulse is generated)

tI2SXKL

0.6

—

μs4

Data setup time

tI2DVKH

100

—

Data input hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

μs2

Data output delay time:

tI2OVKL

—0.9

—

Set-up time for STOP condition

tI2PVKH

0.6

—

μs—

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs—

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OVDD

—V

—

Noise margin at the HIGH level for each connected

device (including hysteresis)

VNH

0.2

× OVDD

—V

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8548E provides a delay time of at least 300 ns for the SDA signal (refer to the VIH(min) of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

When MPC8548E acts as the I2C bus master while transmitting, MPC8548E drives both SCL and SDA. As long as the load

on SCL and SDA are balanced, MPC8548E would not cause unintended generation of Start or Stop condition. Therefore,

the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required

for MPC8548E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure

both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock

frequency is 400 kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of

0x10 (decimal 16):

I2C source clock frequency

333 MHz

266 MHz

200 MHz

133 MHz

FDR bit setting

0x2A

0x05

0x26

0x00

Actual FDR divider selected

896

704

512

384

Actual I2C SCL frequency generated

371 kHz

378 kHz

390 kHz

346 kHz

For the detail of I2C frequency calculation, refer to Freescale Application Note AN2919,

Determining the I2C Frequency

Divider Ratio for SCL. Note that the I2C source clock frequency is half of the CCB clock frequency for MPC8548E.

3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. Guaranteed by design.

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