MPC8536AVTATH datasheet(116/128 Pages) FREESCALE

116 / 128 page

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Pin States in Deep Sleep State

Freescale Semiconductor

116

3.3

Pin States in Deep Sleep State

In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain

enabled.

The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable

the receivers of input pads as defined in Table 1. See the MPC8536E PowerQUICC™ III Integrated Processor Reference

Manual

for details.

3.4

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high

frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching

other components in the MPC8536E system, and the device itself requires a clean, tightly regulated source of power. Therefore,

it is recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD,

and LVDD pin of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD, OVDD,

GVDD, and LVDD, and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors

must be placed directly under the device using a standard escape pattern as much as possible. If some caps are to be placed

surrounding the part it should be routed with short and large trace to minimize the inductance.

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to

minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD,

BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should

have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected

to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types

and quantity of bulk capacitors.

3.5

SerDes Block Power Supply Decoupling Recommendations

he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnVDD and XnVDD) to ensure low jitter on

transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to

power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls

of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and

ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the

device as close to the supply and ground connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SnVDD and XnVDD) to the board

ground plane on each side of the device. This should be done for all SerDes supplies.

•

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance

(ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all

SerDes supplies.

3.6

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active

low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be

connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all

external VDD,TVDD, BVDD, OVDD, GVDD, and LVDD and GND pins of the device.

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