MPC8536AVTATH datasheet(111/128 Pages) FREESCALE

111 / 128 page

Thermal

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

111

2.24.1

Thermal Characteristics

Table 79 provides the package thermal characteristics.

Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material

was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the MPC8536E

thermal model without a lid is shown in Figure 72 The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane

conductivity of 19.8 W/m•K and a through-plane conductivity of 1.13 W/m•K. The solder balls and air are modeled as a single

block 29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/m•K and a through plane conductivity of 12.1 W/m•K. The

die is modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal

resistance between the die and substrate assuming a conductivity of 7.5 W/m•K in the thickness dimension of 0.07 mm. The die

is centered on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for

actual dimensions.

2.24.2

Recommended Thermal Model

Table 79. Package Thermal Characteristics

Characteristic

JEDEC Board

Symbol

Value

Unit

Notes

Junction-to-ambient Natural Convection

Single layer board (1s)

RθJA

°C/W

1, 2

Junction-to-ambient Natural Convection

Four layer board (2s2p)

RθJA

°C/W

1, 2

Junction-to-ambient (@200 ft/min)

Single layer board (1s)

RθJA

°C/W

1, 2

Junction-to-ambient (@200 ft/min)

Four layer board (2s2p)

RθJA

°C/W

1, 2

Junction-to-board thermal

—

RθJB

°C/W

Junction-to-case thermal

—

RθJC

< 0.1

°C/W

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method

(MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 •C/W

C/W

Table 80. MPC8536E Thermal Model

Conductivity

Value

Units

Die (9.6x9.6

× 0.85 mm)

Silicon

Temperature dependent

—

Bump/Underfill (9.6 x 9.6

× 0.07 mm) Collapsed Thermal Resistance

7.5

W/m•K

Substrate (29

× 29 × 1.2 mm)

19.8

W/m•K

19.8

1.13

MPC8536AVTATH датащи(PDF) 111 Page - Freescale Semiconductor, Inc

MPC8536AVTATH датащи(HTML) 111 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL