MPC5634M datasheet(19/118 Pages) FREESCALE

19 / 118 page

Overview

MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by

output of second time base prescaler

— Second time base counter can work as a continuous angle counter, enabling angle based applications to match

angle instead of time

— Both time bases can be exported to the eMIOS timer module

— Both time bases visible from the host

•

Event-triggered microengine:

— Fixed-length instruction execution in two-system-clock microcycle

— 14 KB of code memory (SCM)

— 3 KB of parameter (data) RAM (SPRAM)

— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected

combinations

— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,

bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign

extension and conditional execution

— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,

and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands

•

Resource sharing features support channel use of common channel registers, memory and microengine time:

— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,

host-configured priority

— Automatic channel context switch when a “task switch” occurs, i.e., one function thread ends and another begins

to service a request from other channel: channel-specific registers, flags and parameter base address are

automatically loaded for the next serviced channel

— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or

inter-channel

— Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines

— Dual-parameter coherency hardware support allows atomic access to two parameters by host

•

Test and development support features:

— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware

breakpoints and watchpoints on several conditions

— Software breakpoints

— SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently

with eTPU2 normal operation

For MPC5634M, the eTPU2 has been further enhanced with these features:

•

System enhancements

— Timebases and channels are run at full system clock speed

— Software watchdog with programmable timeout

— Real-time performance information

•

Channel enhancements

— Programmable channel mode allows customization of channel function

— Channels 1 and 2 can optionally drive angle clock hardware

•

Programming enhancements

— Engine relative addressing mode

— More flexibility in requesting DMA and interrupt service

— Channel flags cannot be tested

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